22 lines
421 B
Systemverilog
22 lines
421 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2020 Stefan Wallentowitz
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// SPDX-License-Identifier: CC0-1.0
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module t();
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logic din [0:15];
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array_test array_test_inst(.din(din));
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initial begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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module array_test(
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input din [0:15]
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);
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endmodule
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