167 lines
3.6 KiB
Systemverilog
167 lines
3.6 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// Based on code Copyright (C) 2019-2021 The SymbiFlow Authors.
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// SPDX-License-Identifier: ISC
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`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0);
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module t;
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initial begin
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int x;
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bit flag = 1;
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int switch = 1;
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int break_on = 1;
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static int return_on = 1;
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x = 0;
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randsequence(main)
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main : first second done;
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first : { x = x + 1; };
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second : { x = x + 2; };
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done : { x = x + 3; };
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endsequence
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`checkd(x, 6);
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x = 0;
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randsequence(main)
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main : or_first | or_second;
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or_first : { x += -2; };
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or_second : { x += 2; };
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endsequence
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if (x != 2 && x != -2) $stop;
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x = 0;
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randsequence(main)
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main : or_first := 1 | or_second := 0;
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or_first : { x += 2; };
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or_second : { x += -2; };
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endsequence
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`checkd(x, 2);
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x = 0;
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flag = 1;
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randsequence(main)
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main : first;
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first : { if (flag) x = 10; else x = 5; };
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endsequence
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`checkd(x, 10);
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x = 0;
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flag = 0;
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randsequence(main)
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main : first;
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first : { if (flag) x = 10; else x = 5; };
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endsequence
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`checkd(x, 5);
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x = 0;
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flag = 1;
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randsequence(main)
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main : first;
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first : if (flag) second else third;
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second : { x = 10; };
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third : { x = 5; };
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endsequence
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`checkd(x, 10);
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x = 0;
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switch = 1;
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randsequence(main)
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main : case (switch)
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0 : zero;
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1 : first;
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2 : second;
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default : third;
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endcase;
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zero : { x = 0; };
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first : { x = 10; };
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second : { x = 2; };
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third : { x = 3; };
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endsequence
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`checkd(x, 10);
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x = 0;
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randsequence(main)
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main : first;
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first : repeat(10) second;
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second : { x = x + 1; };
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endsequence
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`checkd(x, 10);
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x = 0;
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randsequence(main)
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main : rand join first second;
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first : { x = x + 20; };
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second : { x = x - 10; };
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endsequence
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`checkd(x, 10);
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x = 0;
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randsequence(main)
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main : rand join (0.5) first second;
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first : { x = x + 20; };
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second : { x = x - 10; };
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endsequence
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`checkd(x, 10);
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x = 0;
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break_on = 1;
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randsequence(main)
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main : first second third;
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first : { x = x + 10; };
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second : { if (break_on == 1) break; } fourth;
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third : { x = x + 10; };
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fourth : { x = x + 15; };
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endsequence
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`checkd(x, 10);
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x = 0;
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break_on = 0;
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randsequence(main)
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main : first second third;
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first : { x = x + 10; };
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second : { if (break_on == 1) break; } fourth;
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third : { x = x + 10; };
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fourth : { x = x + 15; };
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endsequence
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`checkd(x, 35);
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x = 0;
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return_on = 1;
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randsequence(main)
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main : first second third;
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first : { x = x + 20; };
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second : { if (return_on == 1) return; x = x + 10; };
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third : { x = x + 5;};
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endsequence
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`checkd(x, 25);
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x = 0;
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return_on = 0;
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randsequence(main)
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main : first second third;
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first : { x = x + 20; };
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second : { if (return_on == 1) return; x = x + 10; };
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third : { x = x + 5;};
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endsequence
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`checkd(x, 35);
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`ifndef VERILATOR // Unsupported randsequence functions
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x = 0;
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randsequence(main)
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main : first second third;
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first : add(10);
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second : add(5);
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third : add(2);
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void add(int y) : { x = x + y; };
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void add(int y) : sub_a sub_b; // This is presumably legal, try it
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endsequence
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`checkd(x, 17);
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`endif
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$finish;
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end
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endmodule
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