72 lines
2.2 KiB
Systemverilog
72 lines
2.2 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// Copyright 2023 by Wilson Snyder. This program is free software; you can
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// redistribute it and/or modify it under the terms of either the GNU
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// Lesser General Public License Version 3 or the Perl Artistic License
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// Version 2.0.
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// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0);
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`define check_range(gotv,minv,maxv) do if ((gotv) < (minv) || (gotv) > (maxv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d-%0d\n", `__FILE__,`__LINE__, (gotv), (minv), (maxv)); $stop; end while(0);
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`define check_within_30_percent(gotv,val) `check_range((gotv), (val) * 70 / 100, (val) * 130 / 100)
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module t;
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localparam int COUNT = 1000;
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int x;
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int seq;
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int counts[8];
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task prep();
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for (int i = 0; i < COUNT; ++i) counts[i] = 0;
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endtask
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initial begin
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prep();
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// rand join
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x = 0;
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randsequence(main)
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main : rand join first second;
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first : { x = x + 20; };
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second : { x = x - 9; } { x = x - 1; };
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endsequence
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`checkd(x, 10);
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prep();
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for (int i = 0; i < COUNT; ++i) begin
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randsequence(main)
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main: rand join count_1 count_2;
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count_1: { ++counts[1]; };
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count_2: { ++counts[2]; };
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endsequence
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end
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`check_within_30_percent(counts[1], COUNT * 1 / 1);
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`check_within_30_percent(counts[2], COUNT * 1 / 1);
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// rand join weight (TODO weight not tested yet)
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prep();
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for (int i = 0; i < COUNT; ++i) begin
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randsequence(main)
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main: rand join (1.0) count_1 count_2;
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count_1: { ++counts[1]; };
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count_2: { ++counts[2]; };
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endsequence
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randsequence(main)
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main: rand join (0.0) count_3 count_4;
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count_3: { ++counts[3]; };
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count_4: { ++counts[4]; };
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endsequence
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end
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`check_within_30_percent(counts[1], COUNT * 1 / 1);
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`check_within_30_percent(counts[2], COUNT * 1 / 1);
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`check_within_30_percent(counts[3], COUNT * 1 / 1);
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`check_within_30_percent(counts[4], COUNT * 1 / 1);
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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