Geza Lore 185e5d8f42 Make 'bit', 'logic' and 'time' types unsigned by default ... IEEE 1800-2017 6.11.3 says these types are unsigned. Until now these types were treated as not having a signedness (NOSIGN), and nodes having these types were later resolved by V3Width to be unsigned. This is a bit problematic when creating nodes of these types after V3Width. Treating these types as unsigned from the get go is fine, and actually improves generated code slightly.		2021-11-09 21:54:21 +00:00
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t	Make 'bit', 'logic' and 'time' types unsigned by default	2021-11-09 21:54:21 +00:00
.gdbinit	…
.gitignore	Ignore some files generated by modelsim (#2669)	2020-12-05 21:55:56 -05:00
CMakeLists.txt	Add TRACE_THREADS to CMake (#2934)	2021-05-08 08:18:08 -04:00
Makefile	Copyright year update	2021-01-01 10:29:54 -05:00
Makefile_obj	Remove unused CFG_CXXFLAGS_STD_OLDEST	2021-09-26 16:01:25 -04:00
driver.pl	Internal coverage: Fix some test runs having conflicting sources.	2021-10-05 20:22:29 -04:00
input.vc	Internal coverage improvements	2020-09-18 21:27:36 -04:00
input.xsim.vc	…