19 lines
488 B
Systemverilog
19 lines
488 B
Systemverilog
// DESCRIPTION: Verilator: Test of select from constant
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//
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// This tests issue #509, bit select of constant fails
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2012 Jeremy Bennett
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// SPDX-License-Identifier: CC0-1.0
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module t;
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// a and b are arrays of length 1.
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wire a[0:0]; // Array of nets
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wire b[0:0];
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assign a = 1'b0; // Only net assignment allowed
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assign b = a[0]; // Only net assignment allowed
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endmodule
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