80 lines
2.2 KiB
Systemverilog
80 lines
2.2 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module - Edge case: multiple instances
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// This file ONLY is placed into the Public Domain, for any use, without warranty.
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// SPDX-License-Identifier: CC0-1.0
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// Test: Multiple instances of same covergroup type sampling the same coverpoint
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// Expected: Each instance tracks coverage independently, achieving same coverage
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// since they all sample the same expression (value1)
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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logic [2:0] value1;
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covergroup cg;
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cp: coverpoint value1 {
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bins low = {[0:3]};
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bins high = {[4:7]};
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}
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endgroup
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// Create three independent instances
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cg cg_inst1 = new;
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cg cg_inst2 = new;
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cg cg_inst3 = new;
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int cyc = 0;
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always @(posedge clk) begin
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cyc <= cyc + 1;
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case (cyc)
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0: begin
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value1 <= 1; // low bin for all instances
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end
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1: begin
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value1 <= 6; // high bin for all instances -> 100%
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end
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2: begin
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begin
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real cov1, cov2, cov3;
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cov1 = cg_inst1.get_inst_coverage();
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cov2 = cg_inst2.get_inst_coverage();
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cov3 = cg_inst3.get_inst_coverage();
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$display("Instance 1 coverage: %f%%", cov1);
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$display("Instance 2 coverage: %f%%", cov2);
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$display("Instance 3 coverage: %f%%", cov3);
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// All instances sample the same coverpoint (value1), so they should all be 100%
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// This tests that multiple instances track coverage independently,
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// even when sampling the same expression
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if (cov1 >= 99.0 && cov2 >= 99.0 && cov3 >= 99.0) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end else begin
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$display("ERROR: Coverage mismatch");
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$display(" Expected: inst1=100%%, inst2=100%%, inst3=100%%");
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$display(" Got: inst1=%f%%, inst2=%f%%, inst3=%f%%", cov1, cov2, cov3);
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$stop;
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end
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end
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end
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endcase
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// Each instance samples the same value (value1)
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// But tracks coverage independently
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cg_inst1.sample();
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cg_inst2.sample();
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cg_inst3.sample();
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if (cyc > 10) begin
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$display("ERROR: Test timed out");
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$stop;
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end
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end
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endmodule
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