24 lines
478 B
Systemverilog
24 lines
478 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2026 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t (input clk);
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int value = 0;
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covergroup cg;
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cp: coverpoint value {
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bins low = {[0:5]};
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}
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endgroup
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cg my_cg = new;
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always @(posedge clk) begin
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real cov;
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cov = my_cg.get_inst_coverage();
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my_cg.sample();
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end
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endmodule
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