84 lines
2.2 KiB
Systemverilog
84 lines
2.2 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain
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// SPDX-FileCopyrightText: 2026 Matthew Ballance
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// SPDX-License-Identifier: CC0-1.0
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// Test basic cross coverage functionality
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module t;
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/* verilator lint_off UNSIGNED */
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bit [7:0] addr;
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bit [7:0] cmd;
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covergroup cg;
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// Two coverpoints with 2 bins each
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a: coverpoint addr {
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bins low = {[0:3]};
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bins high = {[4:7]};
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}
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b: coverpoint cmd {
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bins read = {0};
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bins write = {1};
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}
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// 2-way cross creates 4 bins: lowread, lowwrite, highread, highwrite
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c: cross a, b;
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endgroup
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initial begin
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cg cg_inst;
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real cov;
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cg_inst = new();
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// Initially coverage should be 0%
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cov = cg_inst.get_inst_coverage();
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if (cov != 0.0) begin
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$error("Initial coverage should be 0%%, got %0.2f%%", cov);
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end
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// Hit lowread
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addr = 2; cmd = 0;
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cg_inst.sample();
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cov = cg_inst.get_inst_coverage();
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// Should have: a.low(1), b.read(1), c.low_x__read(1) = 3/8 = 37.5%
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if (cov < 35.0 || cov > 40.0) begin
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$error("After 1 sample, expected ~37.5%%, got %0.2f%%", cov);
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end
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// Hit highwrite
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addr = 5; cmd = 1;
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cg_inst.sample();
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cov = cg_inst.get_inst_coverage();
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// Should have: a.low(1), a.high(1), b.read(1), b.write(1),
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// c.low_x__read(1), c.high_x__write(1) = 6/8 = 75%
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if (cov < 70.0 || cov > 80.0) begin
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$error("After 2 samples, expected ~75%%, got %0.2f%%", cov);
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end
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// Hit lowwrite
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addr = 1; cmd = 1;
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cg_inst.sample();
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cov = cg_inst.get_inst_coverage();
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// Should have 7/8 = 87.5%
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if (cov < 85.0 || cov > 90.0) begin
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$error("After 3 samples, expected ~87.5%%, got %0.2f%%", cov);
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end
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// Hit highread for 100% coverage
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addr = 7; cmd = 0;
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cg_inst.sample();
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cov = cg_inst.get_inst_coverage();
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// Should have 8/8 = 100%
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if (cov != 100.0) begin
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$error("After all bins hit, expected 100%%, got %0.2f%%", cov);
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end
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$display("Cross coverage test PASSED - final coverage: %0.2f%%", cov);
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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