60 lines
1.3 KiB
Systemverilog
60 lines
1.3 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty.
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// SPDX-License-Identifier: CC0-1.0
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// Test: Covergroup with clocking event using MODULE INPUT clock
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// Status: WORKS - Verilator correctly auto-samples when clk is a module port
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module t(/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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logic [1:0] data;
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/* verilator lint_off UNSIGNED */
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covergroup cg @(posedge clk);
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cp: coverpoint data {
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bins val0 = {2'b00};
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bins val1 = {2'b01};
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bins val2 = {2'b10};
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bins val3 = {2'b11};
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}
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endgroup
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/* verilator lint_on UNSIGNED */
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cg cg_inst = new;
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int cyc = 0;
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always @(posedge clk) begin
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cyc <= cyc + 1;
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// Change data each cycle
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data <= cyc[1:0];
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if (cyc == 5) begin
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automatic real cov = cg_inst.get_inst_coverage();
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$display("Coverage: %0.1f%%", cov);
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// Should have hit all 4 bins (cycles 0-3) = 100%
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if (cov >= 99.0) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end else begin
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$display("ERROR: Expected 100%% coverage, got %f%%", cov);
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$stop;
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end
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end
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if (cyc > 10) begin
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$display("ERROR: Test timeout");
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$stop;
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end
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end
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endmodule
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