88 lines
2.3 KiB
Systemverilog
88 lines
2.3 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain
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// SPDX-FileCopyrightText: 2026 Matthew Ballance
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// SPDX-License-Identifier: CC0-1.0
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// Test array bins - separate bin per value
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module t;
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/* verilator lint_off UNSIGNED */
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bit [7:0] data;
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covergroup cg;
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coverpoint data {
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// Array bins: creates 3 separate bins
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bins values[] = {1, 5, 9};
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// Non-array bin: creates 1 bin covering all values
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bins grouped = {2, 6, 10};
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}
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endgroup
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initial begin
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cg cg_inst;
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real cov;
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cg_inst = new();
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// Initial coverage should be 0%
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cov = cg_inst.get_inst_coverage();
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if (cov != 0.0) begin
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$error("Expected 0%% coverage, got %0.2f%%", cov);
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end
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// Hit first array bin value (1)
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data = 1;
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cg_inst.sample();
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cov = cg_inst.get_inst_coverage();
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$display("After hitting value 1: %0.2f%%", cov);
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// 1 bin out of 4 total bins (3 array bins + 1 grouped bin)
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if (cov < 23.0 || cov > 27.0) begin
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$error("Expected ~25%% (1/4 bins), got %0.2f%%", cov);
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end
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// Hit second array bin value (5)
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data = 5;
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cg_inst.sample();
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cov = cg_inst.get_inst_coverage();
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$display("After hitting value 5: %0.2f%%", cov);
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// 2 bins out of 4
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if (cov < 48.0 || cov > 52.0) begin
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$error("Expected ~50%% (2/4 bins), got %0.2f%%", cov);
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end
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// Hit the grouped bin (covers all of 2, 6, 10)
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data = 6;
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cg_inst.sample();
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cov = cg_inst.get_inst_coverage();
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$display("After hitting grouped bin: %0.2f%%", cov);
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// 3 bins out of 4
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if (cov < 73.0 || cov > 77.0) begin
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$error("Expected ~75%% (3/4 bins), got %0.2f%%", cov);
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end
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// Hit third array bin value (9)
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data = 9;
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cg_inst.sample();
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cov = cg_inst.get_inst_coverage();
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$display("After hitting value 9: %0.2f%%", cov);
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// All 4 bins covered
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if (cov != 100.0) begin
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$error("Expected 100%% (4/4 bins), got %0.2f%%", cov);
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end
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// Verify hitting other values in grouped bin doesn't increase coverage
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data = 2;
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cg_inst.sample();
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cov = cg_inst.get_inst_coverage();
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if (cov != 100.0) begin
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$error("Coverage should stay 100%%, got %0.2f%%", cov);
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end
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$display("Array bins test PASSED");
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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