58 lines
1.1 KiB
Systemverilog
58 lines
1.1 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 by Marco Bartoli.
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// SPDX-License-Identifier: CC0-1.0
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`define STRINGIFY(x) `"x`"
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module t(
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input clk
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);
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typedef struct packed {
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logic [7:0] x;
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logic [7:0] y;
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} point_t;
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typedef struct packed {
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point_t origin;
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point_t size;
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} rect_t;
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int cyc;
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rect_t rect;
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point_t pt;
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sub #(10) sub_a(.*);
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always @(posedge clk) begin
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cyc <= cyc + 1;
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pt.x <= pt.x + 1;
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pt.y <= pt.y + 2;
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rect.origin.x <= rect.origin.x + 1;
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rect.origin.y <= rect.origin.y + 2;
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rect.size.x <= 8'd100;
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rect.size.y <= 8'd200;
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if (cyc == 5) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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initial begin
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$dumpfile(`STRINGIFY(`TEST_DUMPFILE));
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// Level 1 counts only module nesting, so nested struct members under t
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// are dumped, but sub_a's signals are still excluded.
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$dumpvars(1);
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end
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endmodule
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module sub #(
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parameter int ADD
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)(
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input int cyc
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);
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int value;
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always_comb value = cyc + ADD;
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endmodule
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