37 lines
772 B
Plaintext
37 lines
772 B
Plaintext
$version Generated by VerilatedVcd $end
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$timescale 1ps $end
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$scope module $rootio $end
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$upscope $end
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$scope module t $end
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$var wire 1 * clk $end
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$var wire 32 " cyc [31:0] $end
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$scope module rect $end
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$scope module origin $end
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$var wire 8 # x [7:0] $end
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$var wire 8 $ y [7:0] $end
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$upscope $end
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$scope module size $end
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$var wire 8 % x [7:0] $end
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$var wire 8 & y [7:0] $end
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$upscope $end
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$upscope $end
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$scope module pt $end
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$var wire 8 ' x [7:0] $end
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$var wire 8 ( y [7:0] $end
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$upscope $end
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$scope module sub_a $end
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$upscope $end
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$upscope $end
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$enddefinitions $end
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#0
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b00000000000000000000000000000000 "
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b00000000 #
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b00000000 $
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b00000000 %
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b00000000 &
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b00000000 '
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b00000000 (
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0*
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