59 lines
1.0 KiB
Systemverilog
59 lines
1.0 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 by Marco Bartoli.
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// SPDX-License-Identifier: CC0-1.0
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`define STRINGIFY(x) `"x`"
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module t(
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);
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logic clk;
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int cyc;
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sub #(10) sub_a(.*);
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sub #(20) sub_b(.*);
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initial begin
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clk = 0;
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forever #1 clk = !clk;
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end
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always @(posedge clk) begin
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cyc <= cyc + 1;
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if (cyc == 1) begin
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$dumpfile({`STRINGIFY(`TEST_OBJ_DIR), "/simx1.vcd"});
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$dumpvars(0, sub_b);
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end
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if (cyc == 5) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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initial begin
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$dumpfile({`STRINGIFY(`TEST_OBJ_DIR), "/simx0.vcd"});
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$dumpvars(1, sub_a);
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end
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endmodule
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module sub #(
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parameter int ADD
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)(
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input int cyc
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);
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int value;
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always_comb value = cyc + ADD;
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deep #(ADD + 1) deep_i(.*);
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endmodule
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module deep #(
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parameter int ADD
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)(
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input int cyc
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);
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int inner;
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always_comb inner = cyc + ADD;
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endmodule
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