68 lines
1.8 KiB
Systemverilog
68 lines
1.8 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t;
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int static_loop_cond;
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function logic f_loop_cond();
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return ++static_loop_cond < 8;
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endfunction
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initial begin
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// Basic loop
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for (int i = 0; i < 3; ++i) begin : loop_0
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$display("loop_0 %0d", i);
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end
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// Loop with 2 init/step
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for (int i = 0, j = 5; i < j; i += 2, j += 1) begin : loop_1
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$display("loop_1 %0d %0d", i, j);
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end
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// While loop with non-trivial init
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begin
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automatic int i = 0;
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automatic int j = 5; // Not a variable
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while (i < j) begin : loop_2
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$display("loop_2 %0d %0d", i++, j);
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end
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end
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// Do loop with non-trivial init
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begin
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automatic int i = 5;
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automatic int j = 0; // Not a variable
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do begin : loop_3
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$display("loop_3 %0d %0d", --i, j);
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end while (i > j);
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end
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// Do loop that executes once - replaced by V3Const, not unrolled
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do begin: loop_4
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$display("loop_4");
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end while(0);
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// Loop with inlined function as condition
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static_loop_cond = 0;
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while (f_loop_cond()) begin : loop_5
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$display("loop_5 %0d", static_loop_cond);
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end
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// Self disabling loop in via 'then' branch of 'if'
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begin
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automatic logic found = 0;
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for (int i = 0; i < 10; ++i) begin : loop_6
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if (!found) begin
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$display("loop_6 %0d", i);
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if (i == $c32("5")) begin // Unknown condition
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$display("stopping loop_6"); // This line is important
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found = 1;
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end
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end
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end
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end
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// Done
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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