66 lines
1.1 KiB
Systemverilog
66 lines
1.1 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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// verilog_format: off
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`define stop $stop
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`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
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// verilog_format: on
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module t;
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logic clk;
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logic A, B, C;
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logic reset;
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logic x;
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always #1 clk = ~clk;
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initial begin
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clk = 0;
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reset = 0;
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A = 0;
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B = 0;
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C = 0;
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#10;
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reset = 1;
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#2;
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A = 1;
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#2;
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`checkd(x, 1'b0);
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#2;
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B = 1;
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#2;
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`checkd(x, 1'b0);
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#2;
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B = 0;
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C = 1;
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#2;
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`checkd(x, 1'b1);
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#10;
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$finish;
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end
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always_ff @(posedge clk or negedge reset) begin
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if (!reset) begin
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x <= '0;
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end
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else if (A) begin
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unique if (B) begin
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x <= '0;
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end
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else if (C) begin
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x <= '1;
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end
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// This passes:
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// else begin end
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else; // For unique if to not have a false positive
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end
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end
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endmodule
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