22 lines
436 B
Systemverilog
22 lines
436 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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primitive not_u(out, in);
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output out;
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input in;
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table
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0 : 1;
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1 : 0;
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endtable
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endprimitive
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module t (out, in);
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input in;
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output wire out;
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real v = 0.34;
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not_u #(1.145, v) dut_u (out, in);
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endmodule
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