42 lines
740 B
Systemverilog
42 lines
740 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t (
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input clk
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);
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int cyc;
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wire integer value_at_top = cyc; // Magic name checked in .py file
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sub1 sub1a (.*);
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sub1 sub1b (.*);
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always @(posedge clk) begin
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cyc <= cyc + 1;
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if (cyc == 10) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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module sub1 (
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input int cyc
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);
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sub2 sub2a (.*);
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sub2 sub2b (.*);
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sub2 sub2c (.*);
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endmodule
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module sub2 (
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input int cyc
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);
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wire integer value_in_sub = cyc; // Magic name checked in .py file
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endmodule
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