39 lines
781 B
Systemverilog
39 lines
781 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module top;
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event a;
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event b;
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initial begin
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#10;
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->b;
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$display("Sleeping at %0t", $time);
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@(a or b); // This must wake at due to 'a' from the other block
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$display("Waking at %0t", $time);
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if ($time != 20) $stop;
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#10;
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->a;
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->b;
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$display("Sleeping at %0t", $time);
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@(a or b); // This must wake at due to 'a' from the other block
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$display("Waking at %0t", $time);
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if ($time != 40) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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always begin
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@b;
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#10;
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->a;
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end
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endmodule
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