42 lines
657 B
Systemverilog
42 lines
657 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Antmicro.
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// SPDX-License-Identifier: CC0-1.0
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`define checkf function void f(); $printtimescale; $display("%0t", $time); endfunction
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package pkg;
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`checkf;
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endpackage
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checker CHK();
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`checkf;
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endchecker
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program PRG;
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`checkf;
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endprogram
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class CLS;
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static `checkf;
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endclass
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module mod;
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CHK chk();
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PRG prg();
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initial begin
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$printtimescale;
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$display("%0t", $time);
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pkg::f();
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chk.f();
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prg.f();
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CLS::f();
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$finish;
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end
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endmodule
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`timescale 1ns / 10ps
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