31 lines
824 B
Systemverilog
31 lines
824 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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// verilog_format: off
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`define stop $stop
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`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
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// verilog_format: on
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module t;
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localparam int unsigned XLEN = 32;
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string pkt;
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int unsigned idx;
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logic [XLEN-1:0] val;
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int code;
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initial begin
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// All digits after % is to get line coverage in verilated.cpp
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code = $sscanf("P20=4cff0000", "P%h=%80123456789h", idx, val);
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`checkh(code, 2);
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`checkh(idx, 32'h20);
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`checkh(val, 32'h4cff0000);
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$finish;
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end
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endmodule
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