21 lines
475 B
Systemverilog
21 lines
475 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t;
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string s;
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initial begin
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for (int a = 0; a < 3; ++a) begin : a_loop
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s += $sformatf(" a%0d", a); // <--- Error: += is not legal on strings
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s = s + s; // <--- Error: += is not legal on strings
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end
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$stop;
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end
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endmodule
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