36 lines
903 B
Systemverilog
36 lines
903 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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// verilog_format: off
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`define stop $stop
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`define checks(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
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// verilog_format: on
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module t;
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class Cls;
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function void m_uvm_execute_field_op();
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real sa_real[3];
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string s;
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// 5 doesn't match array size of 3
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for (int i = 0; i < 5; ++i) begin
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s = $sformatf("%g", sa_real[i]);
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`checks(s, "0");
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s = $sformatf("%p", sa_real[i]);
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`checks(s, "0");
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end
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endfunction
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endclass
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initial begin
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Cls c;
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c = new;
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c.m_uvm_execute_field_op();
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$finish;
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end
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endmodule
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