29 lines
697 B
Systemverilog
29 lines
697 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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class Cls;
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function int do_randomize();
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int flocal, success;
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success = std::randomize(flocal);
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if (success !== 1) $stop;
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do_randomize = flocal;
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endfunction
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endclass
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module t;
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int r1, r2, r3;
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initial begin
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Cls c;
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c = new;
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r1 = c.do_randomize();
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r2 = c.do_randomize();
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r3 = c.do_randomize();
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$display("%x %x %x", r1, r2, r3);
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if (r1 == r2 && r2 == r3) $stop; // Not impossible but 2^63 odds of failure
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$finish;
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end
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endmodule
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