38 lines
956 B
Systemverilog
38 lines
956 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Aleksander Kiryk.
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// SPDX-License-Identifier: CC0-1.0
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// This test checks if calls to get_randstate don't affect
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// the state of RNG.
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module t;
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integer a1, a2, b1, b2;
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string s1, s2;
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process p;
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initial begin
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p = process::self();
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// 1. Take two random values with get_randstate call in between
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s1 = p.get_randstate();
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a1 = $urandom;
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s2 = p.get_randstate();
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a2 = $urandom;
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// 2. Take two random values again, this time without the call
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p.set_randstate(s1);
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b1 = $urandom;
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b2 = $urandom;
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// The initial state of RNG was restored before step 2., so each
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// corresponding call to $urandom should return the same value.
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if (a1 != b1) $stop;
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if (a2 != b2) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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