134 lines
3.8 KiB
Systemverilog
134 lines
3.8 KiB
Systemverilog
// (C) 2001-2020, Daniel Kroening, Edmund Clarke,
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// Computer Science Department, University of Oxford
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// Computer Science Department, Carnegie Mellon University
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//
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// All rights reserved. Redistribution and use in source and binary forms, with
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// or without modification, are permitted provided that the following
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// conditions are met:
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//
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// 1. Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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//
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// 2. Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the distribution.
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//
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// 3. Neither the name of the University nor the names of its contributors
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// may be used to endorse or promote products derived from this software
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// without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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// POSSIBILITY OF SUCH DAMAGE.
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//
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// You can contact the author at:
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// - homepage : https://www.cprover.org/ebmc/
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// - source repository : https://github.com/diffblue/hw-cbmc
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module t ( /*AUTOARG*/
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// Inputs
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clk,
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reset
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);
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input clk;
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input reset;
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eventually1 eventually1 (.*);
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eventually2 eventually2 (.*);
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sva_implies2 sva_implies2 (.*);
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sva_iff2 sva_iff2 (.*);
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endmodule
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module eventually1 (
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input clk,
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input reset
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);
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// count up from 0 to 10
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reg [7:0] counter;
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initial counter = 0;
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always @(posedge clk) if (counter != 10) counter = counter + 1;
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// expected to pass
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p0 :
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assert property (counter == 1 implies eventually[1: 2] counter == 3);
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endmodule
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module eventually2 (
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input clk,
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input reset
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);
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reg [7:0] counter;
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initial counter = 0;
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always @(posedge clk) counter = 0;
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// expected to fail
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p0 :
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assert property (eventually[0: 2] counter == 3);
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endmodule
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module sva_implies2 (
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input a,
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b
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);
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p0 :
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assert property ((always a) implies (always a));
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p1 :
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assert property ((a or(always b)) implies (a or(always b)));
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p2 :
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assert property ((eventually[0: 1] a) implies (eventually[0: 1] a));
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p3 :
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assert property ((s_eventually a) implies (s_eventually a));
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p4 :
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assert property ((a until b) implies (a until b));
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p5 :
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assert property ((a s_until b) implies (a s_until b));
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p6 :
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assert property ((a until_with b) implies (a until_with b));
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p7 :
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assert property ((a s_until_with b) implies (a s_until_with b));
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p8 :
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assert property ((a |-> b) implies (a |-> b));
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p9 :
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assert property ((a #-# b) implies (a #-# b));
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endmodule
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module sva_iff2 (
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input a,
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b
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);
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p0 :
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assert property ((always a) iff (always a));
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p1 :
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assert property ((eventually[0: 1] a) iff (eventually[0: 1] a));
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p2 :
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assert property ((s_eventually a) iff (s_eventually a));
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p3 :
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assert property ((a until b) iff (a until b));
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p4 :
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assert property ((a s_until b) iff (a s_until b));
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p5 :
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assert property ((a until_with b) iff (a until_with b));
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p6 :
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assert property ((a s_until_with b) iff (a s_until_with b));
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p7 :
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assert property ((a |-> b) iff (a |-> b));
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p8 :
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assert property ((a #-# b) iff (a #-# b));
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endmodule
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