59 lines
1.5 KiB
Systemverilog
59 lines
1.5 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2024 by Josse Van Delm.
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// SPDX-License-Identifier: CC0-1.0
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// verilator lint_off WIDTH
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module m2 #(parameter int N = 4)
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(input [N-1:0] i0, i1,
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input s,
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output [N-1:0] y);
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assign y = s ? i1 : i0;
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endmodule
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module m4 #(parameter int N = 4)
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(input [N-1:0] i0, i1, i2, i3,
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input [1:0] S,
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output [N-1:0] y);
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wire [N-1:0] o_low, o_high;
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// See issue #4920 - use of m4 without parameter overrides
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// caused the other use of m4(#(6)) to irop the #(N) below
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m2 #(N) lowm( .i0(i0), .i1(i1), .s(S[0]), .y(o_low));
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m2 #(N) highm( .i0(i2), .i1(i3), .s(S[0]), .y(o_high));
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m2 #(N) finalm( .i0(o_low), .i1(o_high), .s(S[1]), .y(y));
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endmodule
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module m8 #(parameter int N = 4)
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(input [N-1:0] i0, i1, i2, i3, i4, i5, i6, i7,
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input [2:0] S,
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output [N-1:0] y);
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wire [N-1:0] o_low, o_high;
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m4 #(N) lowm(.i0(i0), .i1(i1), .i2(i2), .i3(i3), .S(S[1:0]), .y(o_low));
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m4 #(N) highm(.i0(i4), .i1(i5), .i2(i6), .i3(i7), .S(S[1:0]), .y(o_high));
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m2 #(N) finalm(.i0(o_low), .i1(o_high), .s(S[2]), .y(y));
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endmodule
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module t ();
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reg [5:0] i0, i1, i2, i3;
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reg [1:0] S;
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wire [5:0] Y;
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m4 #(6) iut(.i0(i0), .i1(i1), .i2(i2), .i3(i3), .S(S), .y(Y));
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initial begin
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i0 = 6'b000000; i1 = 6'b000001; i2 = 6'b000010; i3 = 6'b000100;
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S = 2'b00; #10;
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S = 2'b01; #10;
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$write("*-* All Finished *-*\n");
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end
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endmodule
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