34 lines
704 B
Systemverilog
34 lines
704 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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package s_pkg;
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typedef enum bit [4:0] {MEM_REQ = 5'b00000} P_Type_e;
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endpackage
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package pkg;
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import s_pkg::*;
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virtual class uvm_sequence #(
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type REQ = int
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);
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REQ m_req;
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endclass
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class cls_txn;
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P_Type_e m_type;
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endclass
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class cls_seq extends uvm_sequence #(cls_txn);
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endclass
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class p_mem_seq extends cls_seq;
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virtual task body();
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if (0 == (m_req.randomize() with {m_req.m_type == MEM_REQ;})) begin
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end
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endtask
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endclass
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endpackage
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