93 lines
2.7 KiB
Systemverilog
93 lines
2.7 KiB
Systemverilog
// -*- Verilog -*-
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2008 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t ( /*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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integer cyc = 0;
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reg [63:0] crc;
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reg negate;
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reg enable;
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wire [31:0] datA = crc[31:0];
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wire [31:0] datB = crc[63:32];
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// Predict result
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wire [63:0] muled = (negate ? (-{32'h0, datA} * {32'h0, datB}) : ({32'h0, datA} * {32'h0, datB}));
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reg [63:0] muled_d1;
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reg [63:0] muled_d2;
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reg [63:0] muled_d3;
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reg enable_d1;
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reg enable_d2;
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always @(posedge clk) enable_d1 <= enable;
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always @(posedge clk) enable_d2 <= enable_d1;
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always @(posedge clk) if (enable) muled_d1 <= muled;
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always @(posedge clk) if (enable_d1) muled_d2 <= muled_d1;
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always @(posedge clk) if (enable_d2) muled_d3 <= muled_d2;
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/*AUTOWIRE*/
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// Beginning of automatic wires (for undeclared instantiated-module outputs)
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wire [64:0] product_d3; // From test of t_math_wallace_mul.v
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// End of automatics
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t_math_wallace_mul test ( /*AUTOINST*/
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// Outputs
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.product_d3 (product_d3[64:0]),
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// Inputs
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.clk (clk),
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.enable (enable),
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.negate (negate),
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.datA (datA[31:0]),
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.datB (datB[31:0]));
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integer cycs_enabled;
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initial cycs_enabled = 0;
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// Test loop
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always @(posedge clk) begin
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`ifdef TEST_VERBOSE
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$write("[%0t] cyc==%0d crc=%x a*b=%x wallace=%x\n", $time, cyc, crc, muled_d3,
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product_d3[63:0]);
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`endif
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cyc <= cyc + 1;
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crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
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negate <= cyc[0]; // Toggle negation
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//enable <= 1'b1; // 100% activity factor
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enable <= cyc[4]; // 50% activity factor
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//enable <= cyc[4]&cyc[3]; // 25% activity factor
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if (enable) cycs_enabled = cycs_enabled + 1;
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if (cyc == 0) begin
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// Setup
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crc <= 64'h5aef0c8d_d70a4497;
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end
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else begin
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if (product_d3[63:0] != muled_d3) begin
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$write("[%0t] BAD product, got=%x exp=%x\n", $time, product_d3[63:0], muled_d3);
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$stop;
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end
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if (cyc == 99) begin
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if (crc !== 64'hc77bb9b3784ea091) $stop;
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end
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`ifndef SIM_CYCLES
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`define SIM_CYCLES 99
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`endif
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if (cyc == `SIM_CYCLES) begin
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$write("- Cycles=%0d, Activity factor=%0d%%\n", cyc, ((cycs_enabled * 100) / cyc));
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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end
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endmodule
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