19 lines
430 B
Systemverilog
19 lines
430 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t (
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input [3:1] i3,
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input [4:1] i4,
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output [3:1] o3,
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output [4:1] o4
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);
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// verilator lint_off WIDTHTRUNC,WIDTHEXPAND // after slashes ignored
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assign o3 = i4;
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assign o4 = i3;
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endmodule
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