29 lines
729 B
Systemverilog
29 lines
729 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t;
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event e;
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logic s;
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function void calls_timing_ctl;
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@e; // <--- Bad IEEE 1800-2023 13.4 time-controlling
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fork // <--- Bad IEEE 1800-2023 13.4 time-controlling
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join
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fork // <--- Bad IEEE 1800-2023 13.4 time-controlling
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join_any
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wait (s); // <--- Bad IEEE 1800-2023 13.4 time-controlling
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// TODO wait_order (e);
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// TODO ##
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// TODO expect
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endfunction
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// No warning here
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wire [31:0] #5 __test_wire = 32'd0;
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function void f;
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int x;
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endfunction
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endmodule
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