78 lines
1.2 KiB
Systemverilog
78 lines
1.2 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2010 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t (
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input clk
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);
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integer i;
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reg sync_blk;
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reg sync_blk2;
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reg sync_nblk;
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reg sync2_ok;
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reg sync3_ok;
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reg combo_blk;
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reg combo_nblk;
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always @(posedge clk) begin
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sync_blk = 1'b1;
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sync_blk2 = 1'b1; // Only warn once per block
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sync_nblk <= 1'b1;
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end
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always_comb begin
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combo_blk = 1'b1;
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combo_nblk <= 1'b1;
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end
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always @(posedge clk) begin
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for (int i = 0; i < 20; i++) begin
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sync2_ok <= 1'b1;
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end
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end
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always @(posedge clk) begin
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sync3_ok <= f(sync3_ok);
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end
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function f(input v);
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f = ~v;
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endfunction
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logic single;
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logic array[1:0];
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DoesBlockingAssignA a (
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.clk(clk),
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.out(single)
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);
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DoesBlockingAssignB b (
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.clk(clk),
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.out(array[0])
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);
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endmodule
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module DoesBlockingAssignA (
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input wire clk,
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output reg out
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);
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always @(posedge clk) out = 1;
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endmodule
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module DoesBlockingAssignB (
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input wire clk,
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output reg out
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);
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always @(posedge clk) out = 1;
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endmodule
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