23 lines
453 B
Systemverilog
23 lines
453 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t (
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input logic a,
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input logic [7:0] b,
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output logic [7:0] c
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);
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always_comb begin : p
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c = b;
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if (a) begin : x
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automatic logic [7:0] n;
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n = b;
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n += 8'h01;
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c = n;
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end
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end
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endmodule
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