21 lines
405 B
Systemverilog
21 lines
405 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2022 by Arkadiusz Kozdra.
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// SPDX-License-Identifier: CC0-1.0
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// See also t_interface_virtual.v
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interface QBus();
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endinterface
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module t;
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virtual QBus q8;
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initial begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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