34 lines
695 B
Systemverilog
34 lines
695 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t(b, si, i, li, w3, w4);
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output b; // Output before type
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output si;
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byte b;
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shortint si;
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int i;
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longint li;
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output i; // Output after type
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output li;
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input [2:0] w3;
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wire [2:0] w3;
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wire [3:0] w4;
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input [3:0] w4;
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initial begin
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if ($bits(b) != 8) $stop;
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if ($bits(si) != 16) $stop;
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if ($bits(i) != 32) $stop;
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if ($bits(li) != 64) $stop;
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if ($bits(w3) != 3) $stop;
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if ($bits(w4) != 4) $stop;
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$finish;
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end
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endmodule
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