25 lines
731 B
Systemverilog
25 lines
731 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2020 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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// verilog_format: off
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`define stop $stop
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`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0x exp=%0x (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0);
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// verilog_format: on
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module t;
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real r;
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bit b;
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initial begin
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r = 1492.4;
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`checkh(r inside {[1492 +/- 2]}, 1'b1);
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`checkh(r inside {[1482 +/- 2]}, 1'b0);
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`checkh(r inside {[1490 +%- 10]}, 1'b1);
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`checkh(r inside {[1090 +%- 10]}, 1'b0);
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end
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endmodule
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