27 lines
650 B
Systemverilog
27 lines
650 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module sub;
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/* verilator hier_block */
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parametrized #(.ARG(1)) parametrized1();
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parametrized #(.ARG(2)) parametrized2();
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initial begin
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if (parametrized1.ARG != 1) $stop;
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if (parametrized2.ARG != 2) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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module parametrized #(parameter ARG=0);
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// This is a parametrized non-hier block under a hier block
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endmodule
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module t;
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sub sub();
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endmodule
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