85 lines
2.1 KiB
Systemverilog
85 lines
2.1 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2020-2024 by Yutetsu TAKATSUKASA and Antmicro.
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// SPDX-License-Identifier: Unlicense
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`define HIER_BLOCK /*verilator hier_block*/
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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wire [7:0] out0;
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wire [7:0] out1;
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int count = 0;
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// unpacked array cannot be passed to hierarchical block
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localparam logic UNPACKED[0:1] = '{1'b1, 1'b0};
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sub0 #(UNPACKED) i_sub0(.clk(clk), .in(8'(count)), .out(out0));
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sub1 #(.T(logic[7:0])) i_sub1(.in(out0), .out(out1));
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always_ff @(posedge clk) begin
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// dotted access under hierarchical block is not allowed ...
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$display("%d i_sub0.ff: %d", count, i_sub0.ff);
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$display("%d i_sub0.i_sub.out: %d", count, i_sub0.i_sub.out);
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// ... Except for ports on a dierct hierarchical child
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$display("%d i_sub0.out: %d", count, i_sub0.out);
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$display("%d out1: %d", count, out1);
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if (count == 16) begin
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if (out1 == 15) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end else begin
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$write("Missmatch\n");
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$stop;
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end
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end
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count <= count + 1;
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end
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endmodule
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module sub0 #(
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parameter logic UNPACKED[0:1] = '{1'b0, 1'b1}
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) (
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input wire clk,
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input wire [7:0] in,
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output wire [7:0] out); `HIER_BLOCK
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logic [7:0] ff;
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always_ff @(posedge clk) ff <= in;
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assign out = ff;
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logic [7:0] gg;
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sub0_sub0 i_sub(.in(ff), .out(gg));
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always_ff @(posedge clk) begin
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// dotted access under hierarchical block is not allowed ...
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$display("%m: i_sub.x: %d", i_sub.x);
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// ... Except for ports on a direct hierarchical child
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$display("%m: i_sub.out: %d", i_sub.out);
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end
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endmodule
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module sub1 #(
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parameter type T = logic
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) (
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input wire T in, output wire T out); `HIER_BLOCK
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assign out = in;
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sub1_sub #(T) sub(in, out);
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endmodule
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module sub0_sub0 (
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input wire [7:0] in,
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output wire [7:0] out
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);
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`HIER_BLOCK
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wire [7:0] x = in + 1;
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assign out = x;
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endmodule
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