27 lines
591 B
Systemverilog
27 lines
591 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2012 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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// See bug408
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module top (
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output logic [1:0] q,
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input logic [1:0] d,
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input logic clk
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);
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genvar i;
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assign q[i] = d[i]; // <--- Error: Misusing genvar i
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genvar a, b, c;
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for (a = 0; a < 2; ++a) begin
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if (a);
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for (b = 0; b < 2; ++b) begin
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if (a);
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if (b);
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if (c); // <--- Error: Misusing genvar c
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end
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end
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endmodule
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