21 lines
590 B
Systemverilog
21 lines
590 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t;
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reg [1:0] in;
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wire [2:0] out;
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// verilator lint_off WIDTH
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buf buf1 (out[0], 1); // <--- BAD wrong connection width
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buf buf2[0:0] (out[1], 2'b01); // <--- BAD wrong connection width
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buf buf3[0:0] (out[2], in[1:0]); // <--- BAD wrong connection width
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buf buf4[3:0] (out[2], in[1:0]); // <--- BAD wrong connection width
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initial $stop;
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endmodule
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