24 lines
492 B
Systemverilog
24 lines
492 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2011 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t;
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task a_task;
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input ign;
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endtask
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function void func_calls_task;
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a_task(1'b0); // <--- Bad: Calling task _from_ function
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endfunction
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function void func_ok;
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fork
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a_task(1'b0); // ok, and done in UVM
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join_none
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endfunction
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endmodule
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