32 lines
794 B
Systemverilog
32 lines
794 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Antmicro.
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// SPDX-License-Identifier: CC0-1.0
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`define stop $stop
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`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0)
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typedef struct packed {
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logic sig1;
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logic sig2;
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logic not_forced;
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} s1;
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module t(clk);
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input clk;
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s1 s1inst;
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logic a = 1'b0;
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logic b;
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initial force s1inst.sig1 = a;
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always @(posedge clk) begin
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force s1inst.sig2 = 1'b1;
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force s1inst.sig1 = b;
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`checkh(s1inst.sig1, b);
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`checkh(s1inst.sig2, 1'b1);
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$finish;
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end
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endmodule
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