31 lines
926 B
Systemverilog
31 lines
926 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t;
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wire array1[2:1];
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wire [2:-1] vec;
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integer bad_index = 1;
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parameter P_ONE = 1;
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initial begin
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force array1[P_ONE] = 1'b1; // ok
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release array1[P_ONE]; // ok
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force vec[P_ONE+:1] = 1'b1; // ok
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release vec[P_ONE+:1]; // ok
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// IEEE 1800-2023 10.6.2 [A force] shall not be a bit-select or a
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// part-select of a [non-constant] variable or of a net with a user-defined
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// nettype.
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force array1[bad_index] = 1'b1; // <---- BAD not constant index
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release array1[bad_index]; // <---- BAD not constant index
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force vec[bad_index+:1] = 1'b1; // <---- BAD not constant index
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release vec[bad_index+:1]; // <---- BAD not constant index
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end
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endmodule
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