17 lines
645 B
Plaintext
17 lines
645 B
Plaintext
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2019 by Stefan Wallentowitz.
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// SPDX-License-Identifier: CC0-1.0
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`verilator_config
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sformat -task "mon_scope_name" -var "formatted"
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public_flat_rd -module "sub" -var "in"
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public_flat_rw -module "sub" -var "in_a"
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public_flat_rw -module "sub" -var "in_b" @(posedge t.monclk)
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public_flat_rw -module "sub" -var "fr_a"
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public_flat_rw -module "sub" -var "fr_b" @(posedge t.monclk)
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// Cover other edge declarations
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public_flat_rw -module "sub" -var "fr_chk" @(posedge t.monclk or negedge t.monclk or edge t.monclk)
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