130 lines
3.6 KiB
Systemverilog
130 lines
3.6 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// Copyright 2010 by Wilson Snyder. This program is free software; you can
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// redistribute it and/or modify it under the terms of either the GNU
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// Lesser General Public License Version 3 or the Perl Artistic License
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// Version 2.0.
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// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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integer cyc = 0;
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wire monclk = ~clk;
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int in;
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int in_a;
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int in_b;
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int fr_a;
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int fr_b;
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int fr_a2;
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int fr_b2;
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int fr_chk;
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sub sub (.*);
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// Test loop
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always @ (posedge clk) begin
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`ifdef TEST_VERBOSE
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$write("[%0t] cyc==%0d in=%x sub.in_a=%x sub.in_b=%x fr_a=%x fr_b=%x fr_a2=%x fr_b2=%x fr_chk=%x\n",
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$time, cyc, in, sub.in_a, sub.in_b, fr_a, fr_b, fr_a2, fr_b2, fr_chk);
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`endif
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cyc <= cyc + 1;
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in <= {in[30:0], in[31]^in[2]^in[0]};
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// The inputs to sub will be updated externally on the neg-edge so these
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// don't matter for the result
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in_a <= in_a + 1;
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in_b <= in_b + 1;
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if (cyc==0) begin
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// Setup
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in <= 32'hd70a4497;
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in_a <= 0;
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in_b <= 0;
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end
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else if (cyc<3) begin
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end
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else if (cyc<10) begin
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if (fr_chk != fr_a) $stop;
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if (fr_chk != fr_b) $stop;
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if (fr_chk != fr_a2) $stop;
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if (fr_chk != fr_b2) $stop;
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end
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else if (cyc==10) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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always @(posedge t.monclk) begin
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mon_eval();
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end
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endmodule
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`ifdef ATTRIBUTES
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import "DPI-C" context function void mon_scope_name (input string formatted /*verilator sformat*/ );
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`else
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import "DPI-C" context function void mon_scope_name (input string formatted);
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`endif
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import "DPI-C" context function void mon_register_b(string name, int isOut, int n, int addend);
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import "DPI-C" context function void mon_register_done();
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import "DPI-C" context function void mon_eval();
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module sub (/*AUTOARG*/
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// Outputs
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fr_a, fr_b, fr_a2, fr_b2, fr_chk,
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// Inputs
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in, in_a, in_b
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);
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`systemc_imp_header
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void mon_class_name(const char* namep);
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void mon_register_a(const char* namep, void* sigp, bool isOut, int n, int addend);
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`verilog
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/* verilator lint_off ASSIGNIN */
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`ifdef ATTRIBUTES // Sensitivity list accepted for backward compatibility but ignored
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input int in /*verilator public_flat_rd*/;
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input int in_a /*verilator public_flat_rw @(posedge t.monclk)*/;
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input int in_b /*verilator public_flat_rw*/;
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output int fr_a /*verilator public_flat_rw @(posedge t.monclk)*/;
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output int fr_b /*verilator public_flat_rw*/;
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`else
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input int in;
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input int in_a;
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input int in_b;
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output int fr_a;
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output int fr_b;
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`endif
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output int fr_a2;
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output int fr_b2;
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output int fr_chk;
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/* verilator lint_on ASSIGNIN */
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always @* fr_a2 = in_a + 1;
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always @* fr_b2 = in_b + 1;
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always @* fr_chk = in + 1;
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initial begin
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// Test the naming
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$c("mon_class_name(this->name());");
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mon_scope_name("%m");
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// Scheme A - pass pointer directly
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$c("mon_register_a(\"in\", &", in, ", false, 0, 1);");
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$c("mon_register_a(\"fr_a\", &", fr_a, ", true, 0, 1);");
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$c("mon_register_a(\"in\", &", in, ", false, 1, 0);");
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$c("mon_register_a(\"in_a\", &", in_a, ", true, 1, 0);");
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// Scheme B - use VPIish callbacks to see what signals exist
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mon_register_b("in", 0, 2, 1);
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mon_register_b("fr_b", 1, 2, 1);
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mon_register_b("in", 0, 3, 0);
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mon_register_b("in_b", 1, 3, 0);
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mon_register_done();
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end
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endmodule
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