35 lines
955 B
Systemverilog
35 lines
955 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Geza Lore.
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// SPDX-License-Identifier: CC0-1.0
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`define signal(name, expr) wire [$bits(expr)-1:0] ``name = expr
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module t (
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`include "portlist.vh" // Boilerplate generated by t_dfg_break_cycles.py
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rand_a, rand_b, srand_a, srand_b
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);
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`include "portdecl.vh" // Boilerplate generated by t_dfg_break_cycles.py
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input rand_a;
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input rand_b;
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input srand_a;
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input srand_b;
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wire logic [63:0] rand_a;
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wire logic [63:0] rand_b;
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wire logic signed [63:0] srand_a;
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wire logic signed [63:0] srand_b;
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//////////////////////////////////////////////////////////////////////////
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logic concat_lhs_a;
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logic concat_lhs_b;
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always_comb begin
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{concat_lhs_a, concat_lhs_b} = rand_a[1:0] + rand_b[1:0];
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end
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`signal(CONCAT_LHS, {concat_lhs_a, concat_lhs_b});
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endmodule
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