77 lines
1.5 KiB
Systemverilog
77 lines
1.5 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2022 by Geza Lore.
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// SPDX-License-Identifier: CC0-1.0
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`default_nettype none
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module t(
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input wire [10:0] i,
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input wire [10:0] j [4],
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input wire [10:0] k [4],
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output wire [10:0] o
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);
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logic [10:0] a;
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assign a[3:0] = i[3:0];
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assign a[4:1] = ~i[4:1];
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assign a[3] = ~i[3];
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assign a[8:5] = i[8:5];
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assign a[7:6] = ~i[7:6];
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assign a[9] = i[9];
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assign a[9] = ~i[9];
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assign a[10] = i[10];
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logic [10:0] u [4];
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assign u = j;
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assign u = k;
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logic [10:0] v [4];
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assign v = j;
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assign v[1] = i;
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logic [10:0] w [4];
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assign w[0] = i;
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assign w = j;
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logic [10:0] x [4];
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assign x[3] = i;
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assign x[3][3:2] = ~i[1:0];
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// No warning for w[2]!
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assign x[2][3:2] = ~i[1:0];
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assign x[2][1:0] = ~i[1:0];
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logic [10:0] y;
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always_comb begin
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y = i;
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{y[1:0], y[2:1]} = i[3:0] + 4'd5;
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end
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logic [10:0] z;
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always_comb begin
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z[2:0] = i[2:0];
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z[7:5] = i[7:5];
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end
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always_comb begin
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z[6:4] = i[6:4];
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z[3:1] = i[3:1];
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end
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assign z[10:7] = i[10:7];
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sub sub_1(i);
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assign sub_1.a = i;
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sub sub_2(i);
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assign sub_2.a[10:5] = i[10:5];
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assign sub_2.a[3:0] = i[3:0];
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assign o = a ^ u[3] ^ v[3] ^ w[3] ^ x[3] ^ y ^ z ^ sub_1.a ^ sub_2.a;
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endmodule
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module sub(input wire [10:0] i);
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logic [10:0] a;
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assign a[5:2] = i[5:2];
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endmodule
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