39 lines
843 B
Systemverilog
39 lines
843 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Antmicro.
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// SPDX-License-Identifier: CC0-1.0
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// verilator lint_off COVERIGN
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module t;
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covergroup cg(int var1, int var2 = 42);
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endgroup
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cg cov1 = new(69, 77);
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cg cov2 = new(69);
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int i, j;
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real r;
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function void x();
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cov1.set_inst_name("the_inst_name");
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cov1.start();
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cov1.sample();
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cov1.stop();
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void'(cov2.get_coverage());
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r = cov2.get_coverage();
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r = cov2.get_coverage(i, j);
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// verilator lint_off IGNOREDRETURN
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cov2.get_inst_coverage();
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// verilator lint_on IGNOREDRETURN
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r = cov2.get_inst_coverage(i, j);
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cg::get_coverage();
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r = cg::get_coverage();
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r = cg::get_coverage(i, j);
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endfunction
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endmodule
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