261 lines
8.4 KiB
Plaintext
261 lines
8.4 KiB
Plaintext
// // verilator_coverage annotation
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2008 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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typedef struct packed {logic a;} str_logic;
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module t (/*AUTOARG*/
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// Inputs
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clk, check_real, check_array_real, check_string
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);
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000010 input clk;
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input real check_real; // Check issue #2741
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input real check_array_real [1:0];
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input string check_string; // Check issue #2766
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typedef struct packed {
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union packed {
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logic ua;
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logic ub;
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} u;
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logic b;
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} str_t;
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000001 reg toggle; initial toggle='0;
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logic _under_toggle = toggle; // For --coverage-underscore
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000001 str_t stoggle; initial stoggle='0;
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000010 str_logic strl; initial strl='0;
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union {
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real val1; // TODO use bit [7:0] here
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real val2; // TODO use bit [3:0] here
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} utoggle;
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const reg aconst = '0;
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~000001 reg [1:0][1:0] ptoggle; initial ptoggle=0;
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integer cyc; initial cyc=1;
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~000006 wire [7:0] cyc_copy = cyc[7:0];
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000001 wire toggle_up;
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typedef struct {
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int q[$];
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} str_queue_t;
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str_queue_t str_queue;
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typedef struct packed {
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// verilator lint_off ASCRANGE
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bit [3:5] x;
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// verilator lint_on ASCRANGE
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bit [0:0] y;
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} str_bit_t;
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~000001 str_bit_t str_bit;
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~000001 str_bit_t [5:2] str_bit_arr;
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assign strl.a = clk;
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alpha a1 (/*AUTOINST*/
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// Outputs
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.toggle_up (toggle_up),
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// Inputs
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.clk (clk),
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.toggle (toggle),
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.cyc_copy (cyc_copy[7:0]));
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alpha a2 (/*AUTOINST*/
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// Outputs
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.toggle_up (toggle_up),
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// Inputs
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.clk (clk),
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.toggle (toggle),
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.cyc_copy (cyc_copy[7:0]));
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beta b1 (/*AUTOINST*/
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// Inputs
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.clk (clk),
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.toggle_up (toggle_up));
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off o1 (/*AUTOINST*/
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// Inputs
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.clk (clk),
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.toggle (toggle));
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param#(1) p1 (/*AUTOINST*/
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// Inputs
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.clk (clk),
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.toggle (toggle));
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param#() p2 (/*AUTOINST*/
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// Inputs
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.clk (clk),
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.toggle (toggle));
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mod_struct i_mod_struct (/*AUTOINST*/
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// Inputs
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.input_struct (strl));
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~000001 reg [1:0] memory[121:110];
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wire [1023:0] largeish = {992'h0, cyc};
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// CHECK_COVER_MISSING(-1)
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always @ (posedge clk) begin
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if (cyc != 0) begin
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cyc <= cyc + 1;
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memory[cyc + 'd100] <= memory[cyc + 'd100] + 2'b1;
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toggle <= '0;
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stoggle.u <= toggle;
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stoggle.b <= toggle;
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utoggle.val1 <= real'(cyc[7:0]);
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ptoggle[0][0] <= toggle;
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if (cyc == 3) begin
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str_queue.q.push_back(1);
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toggle <= '1;
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str_bit.x <= '1;
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str_bit.y <= '1;
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str_bit_arr[4].x <= '1;
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end
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if (cyc == 4) begin
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if (str_queue.q.size() != 1) $stop;
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toggle <= '0;
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str_bit.x[3] <= 0;
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str_bit.y[0] <= 0;
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str_bit_arr[4].x[3] <= 0;
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end
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else if (cyc == 10) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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end
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endmodule
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module alpha (/*AUTOARG*/
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// Outputs
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toggle_up,
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// Inputs
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clk, toggle, cyc_copy
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);
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// t.a1 and t.a2 collapse to a count of 2
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000020 input clk;
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000002 input toggle;
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// CHECK_COVER(-1,"top.t.a*","toggle:0->1",2)
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// CHECK_COVER(-2,"top.t.a*","toggle:1->0",2)
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// (t.a1 and t.a2)
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~000012 input [7:0] cyc_copy;
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// CHECK_COVER(-1,"top.t.a*","cyc_copy[0]:0->1",12)
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// CHECK_COVER(-2,"top.t.a*","cyc_copy[0]:1->0",10)
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// CHECK_COVER(-3,"top.t.a*","cyc_copy[1]:0->1",6)
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// CHECK_COVER(-4,"top.t.a*","cyc_copy[1]:1->0",4)
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// CHECK_COVER(-5,"top.t.a*","cyc_copy[2]:0->1",2)
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// CHECK_COVER(-6,"top.t.a*","cyc_copy[2]:1->0",2)
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// CHECK_COVER(-7,"top.t.a*","cyc_copy[3]:0->1",2)
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// CHECK_COVER(-8,"top.t.a*","cyc_copy[3]:1->0",0)
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// CHECK_COVER(-9,"top.t.a*","cyc_copy[4]:0->1",0)
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// CHECK_COVER(-10,"top.t.a*","cyc_copy[4]:1->0",0)
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// CHECK_COVER(-11,"top.t.a*","cyc_copy[5]:0->1",0)
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// CHECK_COVER(-12,"top.t.a*","cyc_copy[5]:1->0",0)
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// CHECK_COVER(-13,"top.t.a*","cyc_copy[6]:0->1",0)
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// CHECK_COVER(-14,"top.t.a*","cyc_copy[6]:1->0",0)
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// CHECK_COVER(-15,"top.t.a*","cyc_copy[7]:0->1",0)
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// CHECK_COVER(-16,"top.t.a*","cyc_copy[7]:1->0",0)
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000002 reg toggle_internal;
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// CHECK_COVER(-1,"top.t.a*","toggle_internal:0->1",2)
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// CHECK_COVER(-2,"top.t.a*","toggle_internal:1->0",2)
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// (t.a1 and t.a2)
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000002 output reg toggle_up;
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// CHECK_COVER(-1,"top.t.a*","toggle_up:0->1",2)
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// CHECK_COVER(-2,"top.t.a*","toggle_up:1->0",2)
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// (t.a1 and t.a2)
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always @ (posedge clk) begin
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toggle_internal <= toggle;
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toggle_up <= toggle;
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end
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endmodule
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module beta (/*AUTOARG*/
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// Inputs
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clk, toggle_up
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);
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000010 input clk;
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000001 input toggle_up;
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// CHECK_COVER(-1,"top.t.b1","toggle_up:0->1",1)
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// CHECK_COVER(-2,"top.t.b1","toggle_up:1->0",1)
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/* verilator public_module */
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always @ (posedge clk) begin
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if (0 && toggle_up) begin end
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end
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endmodule
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module off (/*AUTOARG*/
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// Inputs
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clk, toggle
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);
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// verilator coverage_off
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input clk;
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// CHECK_COVER_MISSING(-1)
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// verilator coverage_on
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000001 input toggle;
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// CHECK_COVER(-1,"top.t.o1","toggle:0->1",1)
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// CHECK_COVER(-2,"top.t.o1","toggle:1->0",1)
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endmodule
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module param #(parameter P = 2) (/*AUTOARG*/
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// Inputs
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clk, toggle
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);
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000010 input clk;
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000001 input toggle;
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~000001 logic z;
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for (genvar i = 0; i < P; i++) begin
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000001 logic x;
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always @ (posedge clk) begin
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x <= toggle;
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end
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for (genvar j = 0; j < 3; j++) begin
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~000002 logic [2:0] y;
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always @ (negedge clk) begin
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y <= {toggle, ~toggle, 1'b1};
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end
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end
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end
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if (P > 1) begin : gen_1
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assign z = 1;
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end
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endmodule
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module mod_struct(/*AUTOARG*/
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// Inputs
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input_struct
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);
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000010 input str_logic input_struct;
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endmodule
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