22 lines
536 B
Systemverilog
22 lines
536 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t;
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class param_comp #(
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type T = bit
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);
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static function int get_type();
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return 0;
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endfunction
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endclass
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class test;
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virtual function void check_phase();
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int m_param_comp_bit_expect_wrapper[string] = '{default: param_comp#(bit)::get_type()};
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endfunction
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endclass
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endmodule
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