88 lines
2.3 KiB
Systemverilog
88 lines
2.3 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module for SystemVerilog 'alias'
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//
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// Simple bi-directional alias test.
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2013 by Jeremy Bennett.
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// SPDX-License-Identifier: CC0-1.0
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// verilog_format: off
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`define stop $stop
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`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0x exp=%0x (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0);
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`define checks(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
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// verilog_format: on
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module t ( /*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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int cyc;
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reg [63:0] crc;
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reg [63:0] sum;
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// Values to swap and locations for the swapped values.
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wire [31:0] x_fwd = crc[31:0];
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wire [31:0] y_fwd;
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wire [31:0] x_bwd;
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wire [31:0] y_bwd = crc[63:32];
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Test test1 (
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.a(x_fwd),
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.b(y_fwd)
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);
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Test test2 (
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.a(x_bwd),
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.b(y_bwd)
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);
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// Test loop
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always @(posedge clk) begin
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`ifdef TEST_VERBOSE
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$write("[%0t] cyc==%0d crc=%x x_fwd=%x y_bwd=%x\n", $time, cyc, crc, x_fwd, y_bwd);
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`endif
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cyc <= cyc + 1;
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crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
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sum <= {x_fwd, y_bwd} ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
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if (cyc == 0) begin
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// Setup
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crc <= 64'h5aef0c8d_d70a4497;
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sum <= '0;
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end else if (cyc < 10) begin
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sum <= '0;
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end else
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if (cyc < 90) begin
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end else if (cyc == 99) begin
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$write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
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`checkh(crc, 64'hc77bb9b3784ea091);
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// What checksum will we end up with (above print should match)
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`checkh(sum, 64'h5a3868140accd91d);
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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// Swap the byte order of two args.
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module Test (
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inout wire [31:0] a,
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inout wire [31:0] b
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);
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alias {a[7:0], a[15:8], a[23:16], a[31:24]} = b;
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// Equivalent to
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// wire [31:0] a_prime;
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// wire [31:0] b_prime;
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// assign b_prime = {a[7:0],a[15:8],a[23:16],a[31:24]};
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// assign {a_prime[7:0],a_prime[15:8],a_prime[23:16],a_prime[31:24]} = b;
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// assign b = b_prime;
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// assign a = a_prime;
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endmodule
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